//五分频 ,占空比为50%
module freq_div5 (
	input clk,    
	input rst_n,
	output logic div_freq_out 
);
	logic nege_capture_R ;
	logic pose_capture_R ;
	logic [2:0] div_cnt_posedge ;
	assign div_freq_out = nege_capture_R | pose_capture_R ;

	always_ff @(posedge clk or negedge rst_n) begin : posedge_capture_always
		if(~rst_n) begin
			pose_capture_R <= 'd0 ;
			div_cnt_posedge <= 'd0 ;
		end else begin
			div_cnt_posedge <= ( div_cnt_posedge == 'd4 ) ? 'd0  : div_cnt_posedge + 'd1 ;
			pose_capture_R <= (div_cnt_posedge == 'd2 || div_cnt_posedge == 'd4) ? ~pose_capture_R : pose_capture_R ;
		end
	end

	always_ff @(negedge clk or negedge rst_n) begin : negedge_capture_always
		if(~rst_n) begin
			nege_capture_R <= 'd0 ;
		end else begin
			nege_capture_R <= pose_capture_R ;
		end
	end

	

endmodule : freq_div5